Turbo/MAP Codec Status Report 23 Aug 1996

This is a short update of what's been happening this last month. The main news to report is that yesterday I finally completed the schematics of the turbo decoder stage and the process of making the printed circuit boards has begun.

Before doing this I re-allocated all the pins on the Xilinx chips to make laying out the board easier. I also eliminated four 74FCT574A flip flop chips by absorbing their function into the Xilinx chip and reducing the number of clock cycles by one (from the previous 13 extra cycles to 12 extra cycles). This was not easy to do since I had to figure out a way of clocking the I/O blocks in the XC3190A Xilinx chips with different clock edges. The solution was to feed in both CLK and CLKB (the inversion of CLK) into the MAP1 Xilinx chips. The data book says that CLKB could be generated internally, but I found that the Xilinx software couldn't do it. I also changed the FFs to latches (which is why I could eliminate a clock cycle). All these changes were successfully implemented on the prototype board.

I was also able to eliminate a clock distribution chip. The FF I used to divide the 20 MHz oscillator signal into square CLK and CLKB clock signals was able to drive all the chips successfully.

The main additions to the printed circuit board schematics was the addition of the delay SRAM for the data and MAP decoders. The miscellaneous Xilinx chip (MAP4) was also modified to produce the SRAM addresses for the data delay.

One change invloved moving some of the connector locations. The decoder didn't work after this change! I quickly located the problem to be due to a short between two of the connector pins. The speedwire board had a bridge between the two pins! Cutting the bridge fixed the problem.

For those of you wanting to see what the prototype boards look like, then go to

http://www.itr.unisa.edu.au/~steven/turbo/codec/

These pictures were made from a Sparc Ultra TV camera (the size of your hand). We now wait for the pcbs to be made up, the boards loaded, and further decoder iterations to be performed!


Steven S. Pietrobon, Satellite Communications Research Centre
University of South Australia, The Levels SA 5095, Australia.
steven@spri.levels.unisa.edu.au http://www.itr.unisa.edu.au/~steven/