The first thing I did before parallel concatenating two rate 1/2 MAP decoders into one iteration of a rate 1/3 turbo decoder was to check why I had to invert the MAP decoder output (see my first MAP decoder report). In my derivation of the MAP decoding algorithm, I had let a binary 0 be mapped to a real -1 and a binary 1 mapped to a real +1. Thus, in two's complement arithmetic, the most significant bit (msb) is a 1 for a negative number and is a 0 for a positive number, opposite to my original assumption. Thus, my MAP decoder was giving the correct output. I had simply forgotten that I had to invert it.
Since I had made an incorrect assumption on the value of the sign bit, I had to make some minor changes in the two's complement to signed magnitude circuits in MAP2 (since the msb is not inverted in the signed magnitude representation).
With those corrections made, I modified the MAPENC Xilinx chip to parallel concatenate the two rate half encoders into a rate 1/3 encoder. I also delayed the input bit by reversing it in time (since the output from the first MAP decoder is reversed in time). The second MAP decoder would then produce its output correctly (since it reverses in time its input which is reversed in time).
I downloaded the design and voila, it didn't work!!! I got a BER of 0.172 for PRBS, 0.244 for all ones, and 0.0 for all zero's. Well, the all zero's result told me that I was getting my signs right. I then drew up a timing diagram and discovered that the decoding delay of each MAP decoder was N+1, not N as I had thought. This is because it takes N data clock (DCLK) cycles for the first block of data (going forward in time), and then another extra cycle going backward in time. This meant that all my addresses to the second MAP decoder o were out by one DCLK cycle.
I then proceeded to greatly modify my MAP decoder board and Xilinx designs to accomodate the extra cycle. This was unfortunately not an easy task. Halfway through making all the changes I realised that if I have the interleaver RAM between the two MAP decoders, and by clocking the data as soon as it is read from the RAM, the delay would be exact multiple of N (as I thought it originally was). Thus, I have spent the last weeks changing my design back and incorporating the small changes required. This required an extra pin on MAP3 (for the signal to clock the data from the RAM) and the elimination of two 74HC574 chips (which could now be incorporated into the Xilinx chips). I also modified MAP2 so that it did use the "low skew" ACLK buffer anymore and relied totally on the "skew free" GCLK buffer.
After correcting all the wiring changes I tested the MAP decoders with my old designs and found them working as expected. This was good because I made quite a few changes and I was afraid that I might have accidently cut a wire or caused a short somewhere. I then tested my new version of the m = 9, R = 1/4 MAP decoder and found it to give an error ratio of 6.46e-2 instead of 5.51e-2 at 0.0 dB Eb/No. After checking a few simple things (such as that I had the right polynomials and sigma) I remade all the Xilinx bit files with the original CMOS inputs (instead of TTL inputs). It now worked, giving a value of 5.54e-2 which is close enough for me. I somehow doubt that it was the CMOS inputs. More likely, I had used the wrong MAP1 bit file. Anyway, the CMOS inputs have more noise margin and there are no TTL signals so I'll be leaving the inputs as CMOS.
The m = 4, r = 1/2 MAP decoder with all the modifications also successfully worked. At 0.5 dB Eb/No, I got a BER of 5.82e-2, compared to 5.95e-2 in my original measurements.
I have decided to not go ahead with the serial iteration design. A serial iteration design needs only one MAP decoder and will be very slow which kind of defeats all the effort I've put into the current design. Instead, by scraping bits of money here and there I can afford to get the MAP/turbo decoder put onto a printed circuit board (PCB) and buy enough parts for six additional boards. My 6U 19 inch rack can hold a total of 20 decoder boards. I'll be putting in a proposal for an Australian Research Council Small Grant to obtain funding for an additional 13 boards. This will basically allow Berrou's original code to be implemented down to rate 1/7 and at 340 kbit/s to boot!. There will be about 26 MBytes of static RAM for 20 boards.
The first of the 1Mx1 SRAMs have arrived which is really neat. I had a very hard time getting these. They are are used for delaying the received samples.
The paper I mentioned in my last report is now available from
http://www.itr.unisa.edu.au/~steven/turbo/PIMRC96.ps.gz
The next step now is to insert the interleaving RAM's between the two encoders (and decoders). Hopefully, the next report will give results for one stage of turbo decoding.
Steven S. Pietrobon, Satellite Communications Research Centre
University of South Australia, The Levels SA 5095, Australia.
steven@spri.levels.unisa.edu.au
http://www.itr.unisa.edu.au/~steven/