I've built a flexible turbo/MAP codec.
codec.jpg is the 6U high 48 cm rack containing from left to right, the encoder/interface card, turbo/MAP decoder 1, interleaver address delay card 1, turbo/MAP decoders 2 to 5, interleaver address delay card 2, and turbo/MAP decoders 6 and 7. An additional 11 turbo/MAP decoder cards can fit within the rack to give a total of 18 iterations. Turbo/MAP decoder 7 has its switches in the up position, indicating the decoder is set up for seven iterations.
pcb.jpg is the printed circuit board of the prototype turbo/MAP decoder. The configuration is similar to Board 2 below. The bottom left Xilinx chip is MAP4 and the bottom right Xilinx chip is MAP2. Between these chips are the 16Kx4 SRAMs for delaying the input and producing the extrinsic information. The 12 SRAMs at the bottom left of the board are for delaying the n 6-bit inputs (six 256Kx1 and six 1Mx1 SRAMs). The four 64Kx4 SRAMs at the bottom right hand corner perform the deinterleaving and interleaving of the data.
board1.jpg is the prototype turbo encoder board. On the left hand side you can see the seven DIP switches used to select the code polynomials. The divisor polynomial is the same for both encoders which can vary from rate 1/2 to rate 1/4. The lsb and msb of the polynomials are set to 1. The number of code states can vary from 4 to 512 states. The bottom Xilinx chip is the encoder, with the interleaver EPROMs directly above it. The interleaver size can vary from 1 to 65536 bits. On the right hand side of the encoder Xilinx chip are some logic and SRAM used to perform the interleaving. To the left hand side we have some logic and a phase locked loop to generate an n times clock from the data clock.
The Xilinx chip in the middle of the board is used to control and generate the SRAM addresses in the interleaver/deinterleaver address generator (IDAG) in the top right corner of the board. The four large chips are the interleaver EPROMS (at left) and deinterleaver EPROMs (at right). Below the EPROMs are the 64Kx4 SRAMs used to store the IDAs.
board2.jpg is the prototype turbo decoder stage. From the top, the Xilinx chips are the branch metric calculator (BMC), control logic and address generator, MAP decoder 1, MAP decoder 2, and the data delay address generator and miscellaneous logic chip. The large chips to the left and right of the Xilinx chips are 1Kx8 dual-port SRAMs used to store the new and old state metrics (SM). The left chips store forward SMs and the right chips store the reverse SMs. To the left of the BMC Xilinx chip are the 64Kx4 SRAMs where we store the branch metrics to be used in calculating the reverse SMs. The four 64Kx4 SRAMs to the right of the BMC chip are used to store the forward SMs to be used in calculating the log-likelihood ratio. The other two 64Kx4 SRAMs to the right are the interleaver RAMs between the two MAP decoders. This prototype does not include the deinterleaver and data delay SRAMs.