Before implementing the second MAP decoder, I decided to investigate the first MAP decoder a little closer. I wasn't happy with the 0.08 dB implementation loss at low BER for the rate 1/2 16 state code. I examined the data signal lines, but they were OK. Next, I examined the noise generator a little closer. I made the PC generate alternating 0's and 1's and discovered that the noise was not reliable on the rising edge of the clock (when I clocking the noise in). I modified my circuit so that I fed a non-inverted clock into the PC, so that the noise would be stable on the rising edge. Performing my simulation results again I found that the implementation loss was reduced to 0.05 dB. A plot of these results can be found in
http://www.itr.unisa.edu.au/~steven/turbo/codec/map24t.ps
If a sequence end's in unknown state (as the second MAP decoder will) some author's have suggested that you should make the first beta equal to the last alpha (for each state). Examining the equations, you can see that beta only depends on future information. Thus, if you end up in an unknown state and you don't know the future (since there isn't any) then theoretically the first beta's should be all the same. Mark Reed, a Ph.D. student here, did some simulations which confirmed my suspicions. This was good news for me, as it made modifying MAP1 simpler (only an extra pin and an AND gate was required). We've submitted a paper on this to Electronic's Letters (which I'll try and make available at our web page soon).
I simulated the MAP decoder at 3.0 dB with the first beta's equal to all zero's (instead of zero for state 0 and 255 for the other states). I measured 1.83e-3 for knowing the final state and 1.84e-3 for not knowing the final state. There does not seem to be much discernable difference between the schemes. This is probably due to the long block size (N = 4096).
After all this was done I finally implemented the second MAP decoder. All the address lines to the RAM's had previously been wired which made things a little easier. With the wiring additions done and extra chips on the board (now totalling 28 chips on the decoder board) I down-loaded the Xilinx bit stream and got zero errors with no noise! I then tested the second MAP decoder at 0.5 dB Eb/No and got 5.93e-2, compared to 5.95e-2 for the first MAP decoder.
So things are proceeding very smoothly. The next step is to parallel concatenate the two decoders (with no interleaving) to form a rate 1/3 decoder.
Steven S. Pietrobon, Satellite Communications Research Centre
University of South Australia, The Levels SA 5095, Australia.
Steven.Pietrobon@unisa.edu.au
http://www.itr.unisa.edu.au/~steven/